(a) Field of the Invention
The present invention relates to a thin film transistor array (TFT) substrate for a liquid crystal display and a method for fabricating the same, and more particularly, to a method for fabricating a TFT array substrate of good performance in processing steps.
(b) Description of the Related Art
Generally, a liquid crystal display (LCD) is formed with two glass substrates, and a liquid crystal layer sandwiched between the substrates.
One of the substrates has a common electrode, a color filter and a black matrix, and the other substrate has pixel electrodes and thin film transistors (TFTs). The former substrate is usually called the xe2x80x9ccolor filter substrate,xe2x80x9d and the latter substrate is usually called the xe2x80x9cTFT array substrate.xe2x80x9d
The TFT array substrate is fabricated by forming a plurality of thin films on a glass substrate, and performing photolithography with respect to the thin films. In photolithography, many masks should be used for uniformly etching the thin films, and this involves complicated processing steps and increased production cost. Therefore, the number of masks becomes a critical factor in the fabrication efficiency of the TFT array substrate.
Furthermore, contact windows tend to be over-etched during the TFT formation, causing contact failure. Thus, it is required that stable and rigid contact between the desired electrodes should be ensured in the device fabrication.
On the other hand, the black matrix provided at the color filter substrate should be formed with a certain width considering the alignment margin for the color filter substrate joining the TFT array substrate. However, the larger black matrix reduces the aperture ratio. Therefore, the opening ratio of the black matrix should be also considered in fabricating the TFT array substrate.
It is an object of the present invention to provide a TFT array substrate for a liquid crystal display of good performance, and a method for fabricating the same with a reduced number of masks.
It is another object of the present invention to provide a method for fabricating a TFT array substrate that ensures suitable contacts between the electrode components.
It is still another object of the present invention to provide a method for fabricating a TFT array substrate with a suitable opening ratio.
These and other objects may be achieved by a TFT array substrate including a gate line assembly with gate lines proceeding in the horizontal direction, gate electrodes branched from the gate lines, and gate pads connected to end portions of the gate lines to receive scanning signals from the outside and transmit them to the gate lines. The gate line assembly may be formed with a single, double or triple layered structure. When the gate line assembly is formed with a double or triple layered structure, one layer is formed with a low resistance material while the other layer is formed with a material having good contact characteristics.
The gate line assembly is overlaid sequentially with a gate insulating layer, semiconductor patterns, and ohmic contact patterns.
A data line assembly is formed on the ohmic contact patterns with data lines proceeding in the vertical direction, data pads connected to end portions of the data lines to receive picture signals from the outside, and source electrodes branched from the data lines. The data line assembly further includes drain electrodes for the TFTs, and conductive patterns for the storage capacitors. The drain electrode is positioned opposite to the source electrode With respect to the gate electrode while being separated from the source electrode. The conductive pattern is positioned above the gate line while overlapping the same. The conductive pattern is connected to a pixel electrode to form a storage capacitor. However, in case the overlapping of the pixel electrode and the gate line can give a sufficient amount of storage capacity, the conductive pattern may be omitted. The data line assembly may have a single, double or triple layered structure.
The semiconductor patterns have a shape similar to that of the data line assembly and the underlying ohmic contact patterns. The semiconductor layer extends to the peripheral portion of the substrate while covering the latter.
A passivation layer covers the data line, the data pad, the source electrode, the drain electrode, the semiconductor pattern, and the overlapping portions between the gate line and the data line.
Contact windows are formed at the passivation layer while exposing the drain electrode and the data pad. The contact window exposing the drain electrode may be extended toward the pixel area such that it can expose the borderline of the drain electrode completely. Another contact window is formed at the passivation layer while passing through the semiconductor pattern and the gate insulating layer to expose the gate pad to the outside.
The pixel electrode is formed on the gate insulating layer at the pixel area defined by the neighboring gate and data lines. The pixel electrode is electro-physically connected to the drain electrode through the contact window such that it receives picture signals from the TFT while making the required electrical field in association with a common electrode. The pixel electrode is extended over the conductive pattern, and electro-physically connected to the latter such that it serves as a storage capacitor together with the conductive pattern and the gate line.
A subsidiary gate pad and a subsidiary data pad are formed on the gate pad and the data pad, respectively. The subsidiary gate and data pads are formed together with the pixel electrode with the same material, and contact the gate and data pads, respectively.
An opening portion may be formed between the pixel electrode and the data line to prevent a possible short circuit thereof.
According to one aspect of the present invention, the steps of fabricating the TFT array substrate may be performed as follows.
A gate line assembly is first formed on a substrate by using a first mask. Then a gate insulating layer, a semiconductor layer, a contact layer, and first and second metal data line layers are deposited onto the substrate with the gate line assembly in a sequential manner. A data line assembly with a predetermined pattern is formed through etching the first and second metal data line layers by using a second mask. The contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly.
A passivation layer is then deposited onto the structured substrate such that the passivation layer covers the semiconductor layer and the data line assembly. A photoresist film is coated onto the passivation layer, and exposed to light by using a third mask. The photoresist film is then developed to thereby form a photoresist pattern partially differentiated in thickness.
A semiconductor pattern is formed by etching the passivation layer and the underlying semiconductor layer at the pixel area through the photoresist pattern. First and second contact windows are formed by etching the passivation layer and the underlying second layers of the drain electrode and the data pad. The third contact window is formed by etching the passivation layer and the underlying semiconductor layer and gate insulating layer, and the second layer of the gate pad.
After the photoresist pattern is removed, a pixel electrode is formed by using a fourth mask such that the pixel electrode is connected to the drain electrode through the first contact window.
The second metal gate or data line layer may be formed with aluminum or aluminum alloy, and the first layer with chrome, molybdenum, or molybdenum alloy. Subsidiary gate and data pads may be formed during the step of forming the pixel electrode such that they are connected to the first layers of the gate and data pads through the second and third contact windows. The pixel electrode as well as the subsidiary gate and data pads may be formed with indium tin oxide or indium zinc oxide.
The etching with respect to the second layers of the drain electrode, the gate pad and the data pad may be performed by using a wet-etching technique or a dry-etching technique.
The step of exposing the passivation layer positioned over the drain electrode and at the pixel area may be performed by removing the photoresist film over the passivation layer through oxygen-based ashing.
The third mask for forming the photoresist pattern may be provided with a transparent substrate, a first layer formed on the transparent substrate, and a second layer formed on the transparent substrate while overlapping with the first layer. The first layer has a light transmissivity lower than the transparent substrate, and the second layer has a light transmissivity different from those of the substrate and the first layer. The transparent substrate is established to have a first portion without the first and second layers, a second portion with only the first layer, and a third portion with both the first and second layers.
The transparent substrate has a light transmissivity of 90%, the first layer has a light transmissivity of 20-40%, and the second layer has a light transmissivity of 3% or less. The first and second layers may have a light transmissivity control pattern of slits or mosaics.
According to another aspect of the present invention, a black matrix and a color filter are formed on the structured substrate before the step of forming the pixel electrode.
After the semiconductor layer is etched to form a semiconductor pattern and the remaining photoresist film is removed, an organic black matrix layer is deposited onto the substrate, and etched through a fourth mask to thereby form a black matrix pattern. Alternatively, a black photoresist film may be used to form such a black matrix pattern.
A color filter is formed at the pixel area between the neighboring data lines, and at that point the formation of the pixel electrode and subsidiary gate and data pads is complete.
According to still another aspect of the present invention, the formation of the passivation layer is deferred after the formation of the semiconductor pattern.
A gate line assembly is first formed at the substrate by using a first mask. A gate insulating layer, a semiconductor layer, an ohmic contact layer, and a metal data line layer are then sequentially deposited onto the substrate. The metal data line layer, the ohmic contact layer and the semiconductor layer are etched through a second mask to thereby form the desired patterns with similar outlines except that the semiconductor pattern is present at the channel region between the source and drain electrodes.
A passivation layer is deposited onto the substrate 10 with the data line assembly, and etched through a third mask to thereby form contact windows. An organic black matrix layer is then deposited onto the substrate, and etched through a fourth mask to thereby form a black matrix pattern. Thereafter, a color filter is formed, and the formation of a pixel electrode and subsidiary gate and data pads is complete.
In the above process, the black matrix pattern may perform the function of the passivation layer without forming the latter. Furthermore, it is also possible that the color filter is placed directly over the substrate and the gate line by removing the portion of the gate insulating layer positioned between the neighboring data lines.